The “Sonoma” Sparc S7 processor takes the S4 core which is similar to Oracle Sparc M7 chip in big NUMA systems. This Oracle chip is more suitable for scale-out two-socket servers that dominate the datacenters of the world. The S7 is to cover scale-out and scale-up systems.
The S4 core has a dual-issue, out-of-order execution unit and has dynamic threading that ranges from one to eight threads per core. Each S4 core has 16 KB of L1 data cache and 16 KB of L1 instruction cache. The M7 and S7 chips organize the cores into clusters of four, and to a certain way of thinking the eight-core S7 is a quarter of a 32-core M7 with InfiniBand and some other features integrated might make it onto the future M8.
Each set of four cores on the S7 chip has a 256 KB L2 instruction cache, and each pair of S4 cores block also has a 256 KB writeback data cache. Both of these L2 caches provide up to 500 GB/sec of bandwidth each.
The four core block on the S7 die has an 8 MB L3 cache, and sports two DDR4 controllers that can support memory running at 2.13 GHz and 2.4 GHz clock speeds. Using 64 GB memory sticks, a two-socket S7 system can have up to 1 TB of main memory and has a peak memory bandwidth of 77 GB/sec. There are also two PCI-Express 3.0 peripheral controllers on the S7 die as well.
The memory latency with the S7 is a little bit lower than for the M7 because the memory controllers are now integrated on the processor. With the M7, the processor had a controller but the buffer chips that actually ran the DDR4 protocol were external to the processor and put on the memory cards like Intel does with the Xeon E7 and IBM does with the Power8.
The S7 will use stock DDR4 memory without buffer chips because the memory controller is on the die. Moreover, because the processor is smaller and has matured the 20 nanometer process that is used to make the S7, its clock speed, at 4.27 GHz, is a little bit higher for the M7, which cycles at 4.13 GHz.
Both have fairly high cycle times compared to Intel Xeons and are in the IBM Power8. The S7 and M7 cores both support eight threads per core, same as the Power8, and four times what Intel supports per core with the Xeons. So the S7 should, core for core, outperform the M7 and, more importantly, give both the Power8 and the Xeon E5 a run for the money in the scale-out datacenter.
The on-chip acceleration includes accelerators for security, encryption, database processing, and analytics that were first etched into transistors with the S4 cores in the M7 processors for high-end Sparc M7 systems.
One important feature in the software-in-silicon stack from Oracle is the ability to transmit fully encrypted virtual machines in Solaris when live migrations occur between two physical machines, and another is the Data Analytics Acceleration, which is an offload engine built onto the chip that does certain kinds of SQL processing common in databases (from Oracle and others) and speeds up the SQL queries by a factor of 10X.
Depending on the workload, we will provide 50 to 100 percent improvement in per core performance compared to the latest generation Broadwell Xeon cores with efficiency, with the offload, and much more bandwidth.
InfiniBand host controller:
The S7 chip was integrated InfiniBand host controller that provides two x4 lanes that run at 56 Gb/sec speeds and that provide a total of 28 GB/sec of bandwidth out of each Sonoma chip.
In a two-socket configuration, both InfiniBand ports can be active, providing dual rail configurations with redundancy and load balancing to get around traffic snarls in the network. But these InfiniBand ports are not activated on the S7 chip, which could mean all of the quirks might not be worked out of them yet.
Oracle is working on its own 100 Gb/sec EDR InfiniBand leaf and fabric switches, based on its own silicon, not that of partner Mellanox Technologies. Oracle is to develop its own 200 Gb/sec HDR InfiniBand switch ASICs, too.
InfiniBand is at the heart of the engineered systems that Oracle sells and InfiniBand to build its public cloud and the clusters.
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