Servers running Intel Xeon Scalable Family processors have six memory channels per processor and up to two DIMMs per channel. To maximize a server’s memory bandwidth and overall performance, it is important to have a balanced memory configuration installed. When incorrectly configured, available memory bandwidth to the server is limited and overall performance can be greatly reduced.
The Intel Xeon Scalable Family processor optimizes memory accesses by creating interleave sets across the memory controllers and memory channels. For each processor, there are two memory controllers. Each memory controller is then attached to three memory channels with up to two DIMMs per channel.
An interleaving set is created when memory channels have the same total memory capacities. If four memory channels have the same total memory capacity and are using identical DIMMs on two memory channels on each memory controller, a 4-way interleave set is created.
In each memory channel, another level of interleaving called “Memory Rank Interleaving” is possible. A DIMM can contain multiple memory ranks, which improves memory performance as the total number of ranks on a memory channel increases. The Intel Scalable Family Processors are optimized for two to four memory ranks per memory channel.
For a balanced memory subsystem the following guidelines should be followed:
2-channel interleave set
This example consists of 2 DIMMs with both populated memory channels with the same memory capacity and the same configuration on each memory controller.
4-channel interleave set
This example consists of 4 DIMMs with four populated memory channels with the same memory capacity and the same configuration on each memory controller.
This example consists of 8 DIMMs with four populated memory channels with the same memory capacity and the same configuration on each memory controller.
6-channel interleave sets
This example consists of 6 DIMMs with six populated memory channels with the same memory capacity and the same configuration on each memory controller.
This example consists of 12 DIMMs with six populated memory channels with the same memory capacity and the same configuration on each memory controller.
Near Balanced Memory configuration that use two different DIMMs and follow all balanced memory guidelines. There are 3% memory loss in memory bandwidth as long as the even number of total memory ranks on each memory channel
Step1: Determine the needed memory capacity
Step 2: Divide by 12 to min. memory DIMM capacity needed
Step 3: Round the value and populate in 12 DIMMs capacity
Each Intel Xeon SP CPU has 6 memory channels, each with up to 2 DIMMs per channel (DPC) supporting a maximum of 12 DIMMs per CPU, or 24 DIMMs per server. While the maximum memory speeds available range from 2133, 2400 or 2666 (depending upon the CPU selected)
There are some general guidelines on how to optimize your memory performance:
In “unbalanced configuration“, the memory is broken up into multiple memory regions creating an environment leading to unpredictable performance.
A configuration of 512 GB on 14G Skylake is possible but suboptimal. Across CPU models (Platinum 8176 down to Bronze 3106), there is a 65% to 35% drop in memory bandwidth when using an unbalanced memory configuration when compared to a balanced memory configuration! The figure compares 512 GB to 384 GB, but the same conclusion holds for 512 GB vs 768 GB as Figure 2 has shown us that a balanced 384 GB configuration performs similarly to a balanced 768 GB configuration.
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